In an active matrix liquid crystal display which displays images by charging pixels through TFTs, some pixels accumulating positive charge and the other pixels accumulating negative charge are mixed together on a display panel when the display panel is driven by applying alternating voltage. Therefore, when the liquid crystal display turns OFF, pixel electrode potential based on counter electrode potential varies depending on the polarity of pixels, accumulating positive charge or negative charge, right before the turning OFF the liquid crystal display device. This tends to cause a leakage of electric charge to a data signal line from a group of pixels, either accumulating positive or negative charge, which has larger potential difference to a potential of data signal line when the liquid crystal display turns OFF. As a result, voltage applied to each of the pixels becomes ununiform, which may cause degradation of the displayed image. Also, in the process of boot up after turning ON the display, electric charge is accumulated to a pixel due to a potential generated in a video signal line or a counter electrode until a logic of a driving circuit is established in the liquid crystal display. This may also cause the image degradation.
As a counter measure to this kind of problem, a conventional configuration illustrated in FIG. 12 is proposed (see Patent Document 1 as an example).
A liquid crystal display device 101 illustrated in FIG. 12 includes a liquid crystal panel 102, a gate driver 103, a source driver 104, a scan signal supply control circuit 105, a data signal supply control circuit 106, and a pixel discharge circuit 107.
The liquid crystal panel 102 is an active matrix display panel including a plurality of scan signal lines GL (1), GL (2), . . . , GL (n), . . . and a plurality of data signal lines SL (1), SL (2), . . . , SL (N), . . . provided so as to be intersected with each other. In each intersection, a pixel PIX is provided. The pixel PIX includes a TFT 102a, a liquid crystal capacitor 102b, and a storage capacitor 102c. A gate terminal of the TFT 102a is connected to a scan signal line GL corresponding to the pixel PIX. One source/drain terminal of the TFT 102a is connected to a data signal line SL corresponding to the pixel PIX. The other source/drain terminal of the TFT 102a is connected to a pixel electrode corresponding to the pixel PIX. The liquid crystal capacitor 102b and the storage capacitor 102c are connected to the pixel PIX between the pixel electrode and a counter electrode COM so as to be parallel to each other.
In the gate driver 103, in response to externally supplied clock signals GCK 1, GCK 2, and a gate start pulse GSP, an internal shift register and a logical circuit generate, at each stage, a signal for producing a scan signal which is to be supplied to a scan signal line GL. In the source driver 104, in response to externally supplied clock signals SCK 1, SCK 2, and a source start pulse signal SSP, an internal shift register generates, at each stage, a signal for producing a controlling signal for an analogue switch B in a data signal supply control circuit 106 (later described).
The scan signal supply control circuit 105 includes a plurality of NAND circuits 105a-1, 105a-2, . . . , 105a-n, . . . , which carry out a NAND operation between the scan signal generated by the gate driver 103 and an externally supplied discharge control signal DIS, provided corresponding to the scan signal lines GL (1), GL (2), . . . , GL (n), . . . , respectively.
The data signal supply control circuit 106 includes a plurality of NAND circuits 106a-1, 106a-2, . . . , 106a-N, . . . , which carry out a NAND operation between the signal generated by the source driver 104 and the externally supplied discharge control signal DIS, provided corresponding to the data signal lines SL (1), SL (2), . . . , SL (N), . . . , respectively. The data signal supply control circuit 106 includes a plurality of CMOS analogue switches B1, B2, . . . , BN, . . . which transform signals generated by NAND circuits 106a-1, 106a-2, . . . , 106a-N, . . . to control signals, respectively. To a gate terminal of a p-channel type MOS transistor of the analogue switch B, a signal generated by a corresponding NAND circuit 106a is directly inputted. To a gate terminal of an n-channel type MOS transistor, a signal generated by a NAND circuit 106a, which is level inverted by an inverters b (inverters b1, b2, . . . , bN, . . . corresponding to the NAND operation circuits 106a-1, 106a-2, . . . , 106a-N, . . . , respectively), is inputted. The analogue switches B1, B2, . . . , BN, . . . are provided corresponding to the data signal lines SL (1), SL (2), . . . , SL (N), . . . , respectively, so as to open and close the connection between the data signal line SL and the video signal line VSIG.
The pixel discharge circuit 107 includes CMOS analogue switches A1, A2, . . . , AN, . . . , which are provided corresponding to the data signal lines SL (1), SL (2), . . . , SL (N), . . . , respectively. As a control signal of the analogue switch A, the discharge control signal DIS is used. To a gate terminal of an n-channel type MOS transistor of the analogue switch A, the discharge control signal DIS, which is level inverted by an inverter a (inverters a1, a2, . . . aN, . . . corresponding to the data signal lines SL (1), SL (2), . . . , SL (N), . . . , respectively), is inputted. To a gate terminal of a p-channel type MOS transistor, the discharge control signal DIS is inputted directly.
The liquid crystal display device 101 with the above configuration, the discharge control signal DIS goes High when the liquid crystal display device 101 is in normal operation. At this time, all the analogue switches A1, A2, . . . AN, . . . turn OFF in union, and each of the analogue switches B1, B2, . . . , BN, . . . in the data signal supply control circuit 106 turns ON sequentially because when the output signal from the stage corresponding to the source driver 104 goes High, the output signal from the corresponding NAND circuit 106a goes Low. Then, the gate driver 103 outputs Low signal from each of the stages sequentially, however, the NAND circuit 105a outputs High scan signal to the corresponding scan signal line GL when the output signal from the stage corresponding to the gate driver 103 goes Low. Accordingly, the pixel PIX which has an ON state TFT 102a is charged by a video signal supplied from the video signal line VSIG via a closed analogue switch B. This realizes image display.
On the other hand, when the liquid crystal display device 101 turns OFF or ON, the discharge signal DIS goes Low right before the turning OFF or ON the display device. Accordingly, all the NAND circuits in the data signal supply control circuit 106, 106a-1, 106a-2, . . . , 106a-N, . . . , output High signal in union, and all the analogue switches B1, B2, . . . , BN, . . . turn OFF in union. Also, all the analogue switches in the pixel discharge circuit 107, A1, A2, . . . , AN, . . . , turn ON in union. Further, all the NAND circuits in the scan signal supply control circuit 105, 105a-1, 105a-2, . . . , 105a-n, . . . , output High signal in union, and all the TFTs 102a in the pixels PIX turn ON in union.
This allows the pixels PIX to discharge all together because the pixel electrode of each pixel PIX is connected to the counter electrode COM (charge from the counter electrode COM in other words). Therefore, each applied voltage to the liquid crystal capacitor 102b and to the storage capacitor 102c of each pixel PIX becomes zero voltage. This can prevent the image degradation when the liquid crystal display device 101 turns ON or OFF.
[Patent Document 1] Japanese Unexamined Patent Publication, Tokukai 2000-347627 (date of publication Dec. 15, 2000)
[Patent Document 2] Japanese Unexamined Patent Publication, Tokukai 2004-45785 (date of publication Feb. 12, 2004)